Verilog vs. VHDL

Verilog -
1984年推出、1995年成為標準IEEE 1364-1995、較廣泛使用、接近程式語言

VHDL (VHSIC Hardware Description Language) -
1983開始、1987年成為標準IEEE 1076-1995、使用較Verilog少、學習時間較Verilog長、仍有其優點

參考資料
Verilog (Wikipedia)
VHDL (Wikipedia)
SystemVerilog (Wikipedia)
Verilog HDL和VHDL的比較

Verilog Development Environment with Mac (Study EECC)

Matlab: Generate a pure tone with *.m file

To play a pure tone (sine wave) in Matlab, type the following code in a new file and save it as genTone.m:

function genTone(Fs, F, time)
t = 0:1/Fs:time;
y = sin(2*pi*F*t);
sound(y,Fs);
end

Now play sound in command

>> genTone(16000,100,0.5);
>> genTone(16000,1000,0.5);

The 3000Hz sound below will be wrong since it is greater than the 4000/2 = 2000 Hz Nyquist frequency.

>> genTone(4000,3000,0.5);

References:

how do i generate sound using MATLAB?
Chapter 2: Practical Audio Processing / tonegen.m (http://mcloughlin.eu/)